Embodiments of the inventive subject matter generally relate to the field of integrated circuit testing, and more particularly to verifying input/output mapping for boundary scan cells.
Boundary scan is a method for testing connections (e.g., wires) on printed circuit boards, and sub-blocks inside integrated circuits. The Joint Test Action Group (JTAG) developed a specification for boundary scan testing. The specification was standardized in 1990 as IEEE Std. 1149.1-1990. The boundary scan architecture provides a means to test interconnects and clusters of logic, memories, and other components without using physical test probes. The boundary scan architecture adds one or more “test cells”, which are connected to each pin of the device. Each test cell can selectively override functionality of a pin to which the test cell is connected. These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board. The cell at the destination of the board trace can then be programmed to read the value at the pin, verifying the board trace properly connects the two pins. If the trace is shorted to another signal, or if the trace has been cut, the correct signal value will not show up at the destination pin, and the board will be observed to have a fault.